基于FPGA的千兆以太网设计详解.docVIP

摘要 随着信息技术的快速发展，以太网嵌入式设备的应用越来越广泛。为了让以太网各设备之间能公平有效地共享通信媒介，对以太网MAC层数据处理系统的研究显得尤为重要。为此，本文首先分析了以太网及其相关协议的基本内涵，解剖了以太网MAC层通信机制、帧的特性与格式、PHY接口协议、ARP协议以及I2C协议。同时通过对FPGA芯片的了解，确定了基于88E1111芯片和XC3S400FPGA芯片相结合的系统设计方案，支持1000Base-T标准以太网的接入，完成了系统的硬件电路设计。系统设计中，88E1111完成PHY层数据的处理，FPGA则完成MAC层数据的处理，主要包含接收MAC数据帧的校验和解封、待发送数据帧的封装、MAC地址滤波、IP数据包的提取、ARP地址映射等，是系统的核心。在FPGA设计中，遵循自上而下的设计思想，对顶层模块以及PHY接口、MAC核心处理、用户配置、用户数据各功能子模块依次进行设计。 ABSTRACT With the rapid development of IT,the embedded devices of accessing to Ethernet are used more and more widely.In order to make each device enjoy a fair and effective shared communications medium, it is particularly important to research the data processing system of the Ethernet MAC layer. To this end,it is firstly done to analyze the basic connotation of Ethernet and the related agreements,and to dissect the communication mechanisms of the Ethernet MAC layer,the characteristics and format of the frame,the PHY interface protocol,the ARP protocol,I2C protocol in the paper.According to the characteristics and working principle of the FPGA chip ,the system design, which supports the accessing of the 1000Base-T Ethernet,is determined based on the combination of the 88E1111 PHY chip and XC3S400-4fg456C FPGA chip of Xilinx.Then the hardware circuit design is accomplished by the Cadence development tool.In this system, 88E1111 and FPGA respectively completes the data processing of PHY layer and the data processing of the MAC layer,which mainly consists of the calibration and dearchive of the receiving data frames, the encapsulation of the data frames,the MAC address filtering, the extraction of the IP packet,The ARP address mapping,and so on. So FPGA is the core of the system. Following the top-down design conception,the design of FPGA successively includes the top-level module,and the submodule of the PHY interface,the MAC core processing,the user configuration,the user data interface. Keywords: Ethernet the MAC layer FPGA 目 录 第一章 绪论 1 1.1研究背景及意义 1 1.2国内外研究现状 2 1