a scalable and reconfigurable priority queue architecture for atm switches：一种可扩展的和可重构的优先级队列架构的自动取款机交换机.pdfVIP

Computer Communications 23 (2000) 333–340 /locate/comcom A scalable and reconfigurable priority queue architecture for ATM switches Yoon-Hwa Choia,*, Pong-Gyou Leeb aDepartment of Computer Engineering, Hongik University, Seoul, South Korea bResearch and Development Center, Locus Corporation, Seoul, South Korea Received 11 September 1998; received in revised form 27 August 1999; accepted 27 August 1999 Abstract Applications with real-time traffic, such as video and voice, require quality-of-service (QoS) guarantees, such as bounded end-to-end delays and bounded cell loss probabilities. In order to provide the QoS guarantees for each connection in ATM networks, link scheduling to prioritize the transmission of queued cells is desirable. A hardware priority queue is then necessary since fast cell switching is hard to be realized in software. In addition, the queue has to be scalable with respect to the number of cells and the number of priority levels. A failure in the priority queue, however, will jeopardize the QoS guarantees for time-critical cells. Moreover, the errors occurred in the queue are unlikely to be detected at the destination. In this paper, we present a fast and scalable priority queue architecture for ATM switches. The queue can reconfigure itself once an error is detected, and thus it will continue normal operation even in the event of a failure. 2000 Elsevier Science B.V. All rights reserved. Keywords : Priority queues; Scalable; Fault; Error detection; Reconfiguration 1. Introduction