数字电路设计课件运算模块设计精要.pptVIP

EE141 EE141 数字集成电路 A Generic Digital Processor Bit-Sliced Design Bit-Sliced Datapath Itanium Integer Datapath Adders Full-Adder The Binary Adder Express Sum and Carry as a function of P, G, D The Ripple-Carry Adder 行波进位加法器延时的结论 传播延时与级数N成线性关系 在设计当前和未来计算机所希望的宽数据通路（N＝32，64，128）加法器时这一点变得日益重要。 在设计一个快速行波进位加法器的全加器单元时，优化tcarry比优化tsum重要的多，因为后者对加法器总延时值的影响较小。 Inversion Property Straight forward implementation:Sum of products Complimentary Static CMOS Full Adder Minimize Critical Path by Reducing Inverting Stages A Better Structure: The Mirror Adder Mirror Adder The Mirror Adder The NMOS and PMOS chains are completely symmetrical. A maximum of two series transistors can be observed in the carry-generation circuitry.(在进位产生电路中最多只有两个晶体管的串连） When laying out the cell, the most critical issue is the minimization of the capacitance at node Co. The reduction of the diffusion capacitances is particularly important. The capacitance at node Co is composed of four diffusion capacitances, two internal gate capacitances, and six gate capacitances in the connecting adder cell . The transistors connected to Ci are placed closest to the output. Only the transistors in the carry stage have to be optimized for optimal speed. All transistors in the sum stage can be minimal size. Transmission Gate Full Adder Manchester Carry Chain Manchester Carry Chain Manchester Carry Chain Carry-Bypass Adder 逻辑设计考虑 Carry-Bypass Adder (cont.) Carry Ripple versus Carry Bypass Carry-Select Adder Carry Select Adder: Critical Path Linear Carry Select Square Root Carry Select Adder Delays - Comparison LookAhead - Basic Idea Look-Ahead: Topology Carry Look Ahead in CMOS? Logarithmic Look-Ahead Adder Carry Lookahead Trees Dot Operator Carry Equation and Dot OPerator Tree Adders Example: Domino Adder Example: Domino Sum 乘法器的基本原理 乘法的示例 乘法的基本形式 M x N位的乘法 生成N个M位的部分积 将这N个部分积 求和生成M+N位最终积 乘法的基本形式 Multiplicand: Y = (yM-1, yM-2, …, y1, y0) Multiplier: X = (xN-1, xN-2, …, x1, x0) Product: 乘法的三种实现模式 乘法器 串行乘法器 并行乘法器 串