简单数字逻辑电路的设计解析.pptVIP

实 验 与 设 计 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY CNT10 IS PORT (CLK,CLR,ENA : IN STD_LOGIC; CO : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); CARRY_OUT : OUT STD_LOGIC ); END CNT10; ARCHITECTURE behav OF CNT10 IS SIGNAL CQI : STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN PROCESS(CLK, CLR, ENA) BEGIN IF CLR = 1 THEN CQI = 0000; ELSIF CLKEVENT AND CLK = 1 THEN IF ENA = 1 THEN IF CQI9 THEN CQI = CQI + 1; ELSE CQI = 0000; END IF; END IF; END IF; END PROCESS; PROCESS(CQI) BEGIN IF CQI=9 THEN CARRY_OUT=1; ELSE CARRY_OUT=0; END IF; END PROCESS; CO=CQI; END behav; LIBRARY IEEE; --32位锁存器 USE IEEE.STD_LOGIC_1164.ALL; ENTITY REG32B IS PORT ( LOAD : IN STD_LOGIC; DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0); DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) ); END REG32B; ARCHITECTURE behav OF REG32B IS BEGIN PROCESS(LOAD, DIN) BEGIN IF LOADEVENT AND LOAD=1 THEN DOUT=DIN;--锁存输入数据 END IF; END PROCESS; END behav; LIBRARY IEEE; --测频控制器 USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY TESTCTL IS PORT (CLK : IN STD_LOGIC; -- 1Hz TSTEN,CLR_CNT,LOAD : OUT STD_LOGIC); END TESTCTL; ARCHITECTURE behav OF TESTCTL IS SIGNAL DIV2CLK : STD_LOGIC; BEGIN PROCESS( CLK ) BEGIN IF CLKEVENT AND CLK = 1 THEN DIV2CLK = NOT DIV2CLK; END IF; END PROCESS; PROCESS (CLK, DIV2CLK) BEGIN IF CLK=0 AND Div2CLK=0 THEN CLR_CNT = 1; ELSE CLR_CNT = 0; END IF; END PROCESS; LOAD = NOT DIV2CLK ; TSTEN = DIV2CLK; END behav; LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY FREQTEST IS PORT(clk : IN STD_LOGIC; FSIN : IN ST