FPGA设计思想与方法(二)精要.ppt

* * * * Data-Path Synchronization Handshaking Signals FIFOs * * Handshaking Data between Clock Domains data_valid acknowledge ready * * FIFO FIFO wr_en rd_en out_data full empty in_data clk * * empty full p_r N p_w p_w p_r p_w p_r 0 Normal almost empty almost full 单元内有数据 单元内无数据 * * Passing Data by FIFO Dual Port Memory Flags: empty,full almost_empty,allmost_full Challenging!! * * FIFO Pointers-Binary Counters * * FIFO Pointers-Gray Counters * * FIFO Design * * Conclusions Partitioning non-synchronizer blocks so that there is only one clock per module permits easy verification of correct timing by creating clock-domain sub-blocks that can be more easily verified with static timing analysis tools. Partitioning synchronizer blocks to permit inputs from one and only one clock domain and clocking the signals with only one asynchronous clock creates manageable synchronizer subblocks that can also be easily timed. A clock-oriented naming convention can be useful to help identify signals that need to be timed within the different asynchronous clock domains. Multiple control signals crossing clock domains require special attention to ensure that all control signals are properly sequenced into a new clock domain. * * 逻辑复制与资源共享的关系 面积与速度的平衡 对立统一的概念 * * 信号敏感表 时序敏感表 组合逻辑的信号敏感表 * * 组合逻辑的信号敏感表 * * 复位逻辑 同步复位逻辑 异步复位逻辑 全局复位逻辑 * * module badFFstyle (q2, d, clk, rst_n); output q2; input d, clk, rst_n; reg q2, q1; always @(posedge clk) if (!rst_n) q1 = 1b0; else begin q1 = d; q2 = q1; end endmodule * * module goodFFstyle (q2, d, clk, rst_n); output q2; input d, clk, rst_n; reg q2, q1; always @(posedge clk) if (!rst_n) q1 = 1b0; else q1 = d; always @(posedge clk) q2 = q1; endmodule * * 同步复位 V.S. 异步复位 同步：工作频率高 异步：设计简单 * * 状态机设计的一般原则 状态机的编码 one-hot消耗触发器多，组合逻辑少：FPGA gray消耗触发器少，组合逻辑多：CPLD 三段式状态机 * * 三段式状态机 三段式建模描述FSM的状态机输出时，只需指定case敏感表为次态寄存器，然后直接在每个次态的case分支中描述该状态的输出即可，不用考虑状态转移条件。 ???三段式描述方法虽然代码结构复杂了一些，但是换来的优势是使FSM做到了同步寄存器输出，消除了组合逻辑输出的不