第4章 存储层次结构设计演示文稿.pptVIP

* * * * * * * * * * * * * * * Branch Predictors that use the behavior of other branches to make a prediction are called correlating predictors or two-level predictors. * * * * * * * * * The University of Adelaide, School of Computer Science * Chapter 2 — Instructions: Language of the Computer * * The University of Adelaide, School of Computer Science * Chapter 2 — Instructions: Language of the Computer * * * * * * * * * * * * * * * * * * * * * Resolve RAW memory conflict? (address in memory buffers) Integer unit executes in parallel * * * * * * Resolve RAW memory conflict? (address in memory buffers) Integer unit executes in parallel * * * * 结构冲突，Mult只有两个保留站 * * * * * * * * * * * * * * * * * Resolve RAW memory conflict? (address in memory buffers) Integer unit executes in parallel * * What you might have thought 1. 4 stages of instruction execution 2. Status of FU: Normal things to keep track of (RAW structura for busyl): Fi from instruction format of the mahine (Fi is dest) Add unit can Add or Sub Rj, Rk - status of registers (Yes means ready) Qj,Qk - If a no in Rj, Rk, means waiting for a FU to write result; Qj, Qk means wihch FU waiting for it 3.Status of register result (WAW WAR)s: which FU is going to write into registers Scoreboard on 6600 = size of FU 6.7, 6.8, 6.9, 6.12, 6.13, 6.16, 6.17 FU latencies: Add 2, Mult 10, Div 40 clocks * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 1.Issue - if no structural haards AND non wAW (no Funtional Unit is going to write this destination register; 1 per clock cycle 2. Read -(RAW) if no instructions is going to write a source register of this instruction (alternatively, no write signal this clock cycle) + gein exection of the instruction; many read ports, so can read many times 3. Execution Complete; multiple during clock cyle 4. Write result - (WAR) If no instructiion is watiing to read the destination register; assume multiple wriite ports; wait for clock cycle to write and tehn read the results; assume c