基于超深亚微米工艺的E-fuse存储电路的设计与研究_new重点分析.docVIP

基于超深亚微米工艺的E-fuse存储电路的设计与研究 E-fuse广泛地应用于超大规模芯片的设计中，在芯片中实现冗余的功能。本文在HUALI 55nm标准CMOS工艺上设计并实现了一个4K 并入并出512 * 8的E-fuse存储电路，八位输出，通过一对放大器模块在控制信号控制其工作与否情况下，分时输出子6位数据信号。放大器模块采用的是交叉耦合的电路结构，并设计4个不同的参考电阻，根据trim过程选择合适的电阻，很好地预防了实际情况下电阻受工艺波动的影响而产生的偏差。同时设计了配套的延迟电路、字线驱动电路等模块。 本文实现的E-fuse阵列在考虑面积、功耗、速度等因素的基础上进行了优化，在设计过程中基于传统的E-fuse单元电路提出了一种新型的单元电路，并在速度、面积、功耗、可靠性等方面进行了对比讨论。电路允许的使用环境波动范围广，其中电压为1.0V-1.4V和2.8V-3.6V，温度由-40℃-125℃，在TT,FF,SS,FS,SF下全部验证通过，功耗最大为11.5mW，读操作的电流小于1.1mA，保证电路的正确读操作，编程电流都在16mA以上，在理论上说明熔丝能够顺利熔断。 本文基于HUALI 55nm标准的CMOS工艺进行整体电路的仿真和对版图的设计，其编程电流典型值为19.5mA，数据输出时间延迟为2nS内，翻转速度小于1.5nS，整体面积为407.652um * 451.8um=0.184mm2，文章的最后给出了部分流片的数据。 关键词：E-fuse，超深亚微米，CMOS Research on and Design of Electrically programmable Fuse (E-Fuse) on Ultra Deep Submicron Abstract E-fuse is widely used as a redundant technology in ULSI. This thesis designs a 4k 512*8 PIPO E-fuse storage circuit, 256 output signals is realized using two groups of 8 data in different time controlled by a pair of amplifiers. The amplifier is constructed using cross coupling differential pair with 4 referential trim resistors. These resistors can be trimmed to accommodate technology fluctuation. The delay module and bit line driving circuit are designed as well. The design is optimized considering area, power, and velocity. A new cell structure is proposed. Its performance of is discussed comparing with traditional structure. The circuit can be operated in a wide range, with voltage from 1.0V to 1.4V and 2.8V to 3.6V, temperature from -40℃ to -125℃. It is verified under TT,FF,SS,FS,SF corner, with minimum power consume 11.5mW，reading current less than 1.1mA. The programming current is larger than 16mA, which can guarantee the triggering of the fuse。 Simulation results show that typical programming current is 19.5mA, delay is less than 2ns, flip time is less than 1.5ns. The chip is realized using HUALI 55nm standard CMOS logic technology. Tapeout data is presented at the end. Keywords: E-fuse, Ultra Deep Submicron, CMOS Writ