本科毕业设计论文--基于jtag的嵌入式故障注入平台.docVIP

毕业设计（论文）题目： 基于JTAG的嵌入式故障注入平台 摘要 业控制交通管理航、航空等关键领域。在这些领域中，嵌入式设备所处的工作环境都比较极端，系统发生故障的概率远比正常高出很多倍。运行于这些关键领域的嵌入式系统如果出现了故障，就可能会巨大的损失。因此需要一种方法能够在嵌入式系统投入实际使用之前对其进行测试模拟实际应用中可能出现的问题可靠性。 本课题设计并实现了一种基于JTAG的嵌入式系统故障注入和分析平台，通过控制其JTAG时序使进入到硬件调试模式中，读写CPU或内存中目标节点的数据注入故障。在硬件调试模式中，目标系统之上的操作系统进入挂起状态暂停运行从硬件调试模式回到正常模式后，操作系统会从挂起前正在执行的指令地址继续向下执行而忽略硬件调试模式中CPU或内存数据的变化这样就达到了绕过操作系统的数据保护限制完成故障注入的目的。 为了实现故障注入的灵活性和对在一个平台上对多种体系结构进行故障注入，本课题使用FPGA芯片作为故障注入目标的运行平台，目标体系结构以软核的形式运行在FPGA芯片中，使用DSP芯片作为故障注入核心控制器，控制测试数据的格式转换、输入输出，与上位机的通信和JTAG时序的控制。 Abstract Because of the adventures such as low power dissipation, high real-time, and scalable of embedded systems, embedded systems have been more and more applied in key areas such as industrial control, traffic management, arms control, aerospace and aviation. In these areas, embedded systems are working in an extremely environment, which caused much higher system failure probability than normal. Failure of the embedded systems in these key areas will cause great loss. Therefore, in order to ensure fault tolerance of the embedded systems work properly, we need a way to evaluate their dependability before they are put into practical use by simulating the situations they will meet. This paper designs and implements a hardware fault injection and analysis platform based on JTAG aimed at embedded systems. Firstly, make the target system enter the hardware debugging mode by controlling its JTAG time series. And secondly, read or write the data in the CPU or memory of the target system. When coming back to normal mode, the operating system will continue to do its work from the point where it entered hardware debugging mode, ignoring the data change in the CPU and memory. In this way, we succeed to bypass the data protection limitation of the operating system and finish fault injection. For the sake of the flexibility of the platform which means suitable for varies of target systems, this paper use FPG