EDA实验四.有限状态机的硬件描述语言设计方法.docVIP

实验四、有限状态机的硬件描述语言设计方法 状态机程序设计 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY shiyanf IS PORT(DIN,CLK,CLR: IN STD_LOGIC; AB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); END shiyanf; ARCHITECTURE ONE OF shiyanf IS SIGNAL Q : INTEGER RANGE 0 TO 8; SIGNAL D : STD_LOGIC_VECTOR(7 DOWNTO 0); BEGIN D PROCESS(CLK,CLR) BEGIN IF CLR =1 THEN Q=0; ELSIF CLKEVENT AND CLK=1 THEN CASE Q IS WHEN 0= IF DIN=D(7) THEN Q=1; ELSE Q=0; END IF; WHEN 1= IF DIN=D(6) THEN Q=2; ELSE Q=0; END IF; WHEN 2= IF DIN=D(5) THEN Q=3; ELSE Q=0; END IF; WHEN 3