集成电路设计图设计剖析.ppt

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EIS-Wuhan University 集成电路设计 第九章 版图设计 outline Floor-Planning Block Placement. Global Routing. Switchbox Routing. 布图规划Floorplanning 输入层次化网表 描述模块间的互联,模块内逻辑单元及互联 逻辑网表—物理描述的转换。 布置模块、焊盘、电源、时钟。 floorplan Floorplanning strategies Floorplanning must take into account blocks of varying function, size, shape. Must design: space allocation; signal routing; power supply routing; clock distribution. Purposes of floorplanning Early in design: Prepare a floorplan to budget area, wire area/delay. Tradeoffs between blocks can be negotiated. Late in design: Make sure the pieces fit together as planned. Implement the global layout. Place and Route Layout synthesis Two critical phases of layout design: placement of components on the chip; routing of wires between components. Placement and routing interact, but separating layout design into phases helps us understand the problem and find good solutions. 布局Placement 根据布图规划,布置模块内逻辑单元。 目标: 可布线 最小延迟 最小尺寸 最小电压衰减 Placement metrics Quality metrics for layout: area; delay. Area and delay determined in part by wiring. How do we judge a placement without wiring? Estimate wire length without actually performing routing. Wire length as a quality metric Wire length measures Estimate wire length by distance between components. Possible distance measures: Euclidean distance (sqrt(x2 + y2)); Manhattan distance (x + y). Multi-point nets must be broken up into trees for good estimates. Placement techniques Can construct an initial solution, improve an existing solution. Pairwise interchange is a simple improvement metric: Interchange a pair, keep the swap if it helps wire length. Heuristic determines which two components to swap. Placement by partitioning Works well for components of fairly uniform size. Partition netlist to minimize total wire length using min-cut criterion. Partitioning may be interpreted as 1-D or 2-D layout. Min-cut bisecting partitioning Min-cut bisecting partitioning Swapping A and B: B drags 1 net; A drags 3 nets; total cut incr

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