EDA工具课程之PrimeTime研讨.ppt

Company Logo 六、实例分析 Company Logo 六、实例分析 clock MY_CLOCK (rise edge)???????????????????????????????????????????? 6.00?????? 6.00 clock network delay (ideal)??????????????????????????????????????????? 2.00?????? 8.00 clock uncertainty?????????????????????????????????????????????????????? -0.50?????? 7.50 S3/P3_reg_47_/CK (DFFTRXL)???????????????????????????????????????????? 0.00?????? 7.50 r library setup time????????????????????????????????????????????????????? -0.28?????? 7.22 data required time?????????????????????????????????????????????????????????????????? 7.22 Critical Path终点的Flip-Flop的时脉输入一样有2ns的network delay，所以本来1个时钟周期后（6ns）要抓取资料就变成了6+2=8ns后抓取资料，也就是Required Time（RT）变成8ns。但因为我们的时脉规格有0.5ns的不确定性（clock uncertainty），以最坏状况考虑，时脉提早了0.5ns到，则RT变為8-0.5=7.5ns。再考量元件库中定义的Setup Time 0.28ns，RT就变為7.5-0.28=7.22ns（下图）。 Company Logo 六、实例分析 data required time?????????????????????????????????????????????????????????????????? 7.22 data arrival time?????????????????????????????????????????????????????????????????? -7.96 -------------------------------------------------------------------------------- slack (VIOLATED)???????????????????????????????????????????????????????????????????? -0.74 有了RT和AT就可以计算slack，这个例子的slack值是负的，也就是无法达到时序规格。由於我们只是要以实例说明STA，时序规格不符合也无所谓。实际制作晶片时，这当然是不允许的。 Company Logo 五、PrimeTime命令简介 时序约束检查 Company Logo 五、PrimeTime命令简介 生成报告 Company Logo 五、PrimeTime命令简介 生成报告 report_timing [-from from_list] [-to to_list] [-through through_list] [-delay_type delay_type] [-nworst paths_per_endpoint] [-max_paths count] [-nets] [-group group_name] [-significant_digits digits] [-nosplit] [-transition_time] [-capacitance] report_bottleneck [-from from_list] [-to to_list] [-through through_list] [-max_cells cell_count] [-max_paths path_count] [-nworst_paths paths_per_endpoint]