AGuidetousetheVCS+Verdifordigitalsystemfunctionsimulation研讨.pptVIP

* 中国科学院通用芯片与基础软件研究中心 CPU and Fundamental Software Research Center A Guide to use the VCS + Verdi for digital system function simulation Ivan.Yam yancy_os@sari.ac.cn 2015/09/18 Agenda VCS Simulation Basics VCS(Verilog Compiled Simulator) Accepts design descriptions in Verilog, SystemVerilog, C/C++ PLI and models Two step simulation process: Step 1: compile (vcs –f sourcefile –Mupdata –l **.log -sverilog) Step 2: run (./simv) VCS Compilation Command Format $ vcs source_file [compile_time_options] Source_file All Verilog/SystemVerilog source files or the DUT Separated multiple source files by spaces Top module should contain test bench for DUT Compile_time_options Control how VCS compiles the source files Critical for optimization for visibility and performance Generates simulation binary executable simv Compile-time option exampiles $ vcs –help Lists compile options, run-time options, environment variables Command line options (commonly used) -Mupdata Incremental compilation (only changed files are compiled) -R Run after compilation -gui Start the DVE gui at runtime -l filename Set log file name -sverilog Enable SystemVerilog language support +v2k Compile with support for Verilog 2001 extensions Compile-time option exampiles Compile-time options to access Verilog library files -v lib_file Search for unresolved module reference in file lib_file -y lib_dir Search for unresolved module reference in file residing in directory lib_dir +libext+lib_ext Use file extension lib_ext when searching for files in library directory lib_dir +incdir+inc_dir Search inc_dir directory for `include filed Compile-time option exampiles Access Verilog file and options via a file -f file File containing a list of absolute pathnames for the source_file and a subset of VCS options User selected simulation binary name -o foo Creates executable foo instead of simv Define a macro +define+macro_name=value VCS Simulation Command Format $ simv [run_time_options] Run_time_option