华南理工大学2013年_数字系统设计(全英)试题A卷答题.doc

《数字系统设计》试卷第  PAGE 12 页 共  NUMPAGES 12 页 姓名 学号 学院 专业 座位号 ( 密 封 线 内 不 答 题 ) ……………………………………………………密………………………………………………封………………………………………线……………………………………线……………………………………… _____________ ________ … 诚信应考,考试作弊将带来严重后果！ 华南理工大学期末考试 《数字系统设计（全英课）》试卷A （2014.1.16） 注意事项：1. 考前请将密封线内各项信息填写清楚； 2. 所有答案请在试卷上答题； 3．考试形式：闭卷； 4. 本试卷共 三 大题，满分100分， 考试时间120分钟。 题 号一二三总分得 分评卷人Multiple choice test（2ⅹ10=20 marks） 1 . Which of the following statements is not true? （ D ） VHDL signal assignment needs a time delay to take effect VHDL signal can be declared in architecture, it’s global VHDL variable assignment takes effect immediately VHDL variable is usually declared in process, it should be included in sensitivity list 2. Which of the following VHDL data types can be used directly， without explicit declaration? （ C ） A. STD_LOGIC ；B. STD_LOGIC_VECTOR；C. BIT；D. ARRAY 3. Which of the following statements on PLD is not true （ B ） A. CycloneII is produced by Altera B. FPGA is based on product terms C. FPGA is field programmable gate array 4. Which of the following statements on sequential circuit is true（ B） A. In synchronous circuit，the actions of Flip-Flops are not necessarily synchronized by the same clock signal B. In asynchronous circuit， the states of Flip-Flops don’t change simultaneously C. The input change of Moore state machine is directly reflected by output 5. Which of the following statements on state machine description is not true ( C ) A．In one-process description style, output can be synchronized B. Two-process description style can avoid unwanted registers C. Two-process description style consumes more resources than one-process description 6. Which of the following statements on metastability is true ( B ) A. In sequential circuit, metastability doesn’t occur if either the set-up time requi