可编程逻辑器件实现三-八译码器摘要.ppt

可编程逻辑器件实现三－八译码器 1.3基于乘积项的CPLD结构 乘积项结构CPLD的逻辑实现原理 CPLD将以下面的方式来实现 硬件描述语言VHDL library IEEE; use IEEE.std_logic_1164.all; entity exp2hdl is port ( K: in STD_LOGIC_VECTOR (3 downto 1));; POUT: out STD_LOGIC_VECTOR (8 downto 1)); end exp2hdl; architecture exp2hdl_arch of exp2hdl is SIGNAL K: STD_LOGIC_VECTOR (3 downto 1); begin PROCESS(K) begin CASE K IS WHEN 000 = POUT WHEN 001 = POUT WHEN 010 = POUT WHEN 011 = POUT WHEN 100 = POUT WHEN 101 = POUT