vlsi circuit design 05 dynamic logic.pptVIP

Dynamic CMOS Logic Dynamic CMOS In static circuits at every point in time (except when switching) the output is connected to either GND or VDD via a low resistance path. fan-in of N requires 2N devices Dynamic circuits rely on the temporary storage of signal values on the capacitance of high impedance nodes. requires only N + 2 transistors takes a sequence of precharge and conditional evaluation phases to realize logic functions Dynamic Gate Dynamic Gate Conditions on Output Once the output of a dynamic gate is discharged, it cannot be charged again until the next precharge operation. Inputs to the gate can make at most one transition during evaluation. Output can be in the high impedance state during and after evaluation (PDN off), state is stored on CL Properties of Dynamic Gates Logic function is implemented by the PDN only number of transistors is N + 2 (versus 2N for static complementary CMOS) should be smaller in area than static complementary CMOS Full swing outputs (VOL = GND and VOH = VDD) Nonratioed - sizing of the devices is not important for proper functioning (only for performance) Faster switching speeds reduced load capacitance due to lower number of transistors per gate (Cint) so a reduced logical effort reduced load capacitance due to smaller fan-out (Cext) no short current Isc, so all the current provided by PDN goes into discharging CL Ignoring the influence of precharge time on the switching speed of the gate, tpLH = 0 but the presence of the evaluation transistor slows down the tpHL Properties of Dynamic Gates, con’t Power dissipation should be better consumes only dynamic power – no short circuit power consumption since the pull-up path is not on when evaluating lower CL- both Cint (since there are fewer transistors connected to the drain output) and Cext (since there the output load is one per connected gate, not two) by construction can have at most one transition per cycle – no glitching But power dissipation can be significantly higher d