第二章CMOS逻辑.pptVIP

ASIC Design CMOS Inverter 2.5? Sequential Logic Cells 建议：采用同步设计 (1)?it allows automated design, (2)?it is safe, (3) it permits vendor signoff (a guarantee that the ASIC will work as simulated) 2.5.1? CMOS Latch 当CLK为高时 透明传输 当CLK为低时 锁存 单元架构 2.5.2? CMOS Flip-Flop ? ? ? 加入反相器作为缓冲输出 * * 第二章：CMOS逻辑 CMOS晶体管 CMOS制作工艺 CMOS设计规则 组合逻辑单元 时序逻辑单元 数据路径逻辑单元 I/O单元 单元编译器（Compilers） × 2.1?CMOS Transistors Polysilicon Aluminum 由N沟和P沟MOS构成 NMOS立体图 图2.3 NMOS的导电机理 耗尽区——导电沟道的形成(VgsVtn)——Ids形成(Vds0) NMOS管的第四端体(bulk－阱或衬底)与地相接，使二极管反偏。 L＝2 Tox=100 angstroms (0.01um micron) Complete Vds vs Ids curve NMOS 萨方程： Idsn = ?n [Vgsn - Vtn]2 / 2 0 Vg - Vtn ? Vdsn Idsn = ?n [(Vgsn - Vtn)Vdsn - Vout2 / 2] Vdsn Vg - Vtn Idsn =0 Vg - Vtn ? 0 Where ?n = ?nEox/tox (Wn/Ln) Current-Voltage RelationsLong-Channel Device （推导过程见书） PMOS 萨方程： Idsp = -?p [Vgsp - Vtp]2 / 2 Vdsp Vg - Vtp Idsp = -?p [(Vgsp - Vtp)Vdsp - Vdsp2 / 2] Vdsp Vg - Vtp Idsp =0 0 ? Vg - Vtp Where ?p= ?pEox/tox (Wp/Lp) 2.1.2:对于深亚微米的MOS管： Ids要比长沟道MOS管小，当电压增加时，甚至只有一半左右！！ First, the threshold voltage is not constant. Second, the actual length of the channel (the electrical or effective length, often written as L eff ) is less than the drawn (mask) length. The third reason is ，electrons cannot move any faster than about v max n = 10 5 ms –1 when the electric field is above 10 6 Vm –1 (reached when 1 V is dropped across 1 um); the electrons become velocity saturated . n-channel transistor characteristics (c) A short-channel transistor shows a more linear characteristic due to velocity saturation. Normally, all of the transistors used on an ASIC have short channels. 2.1.3: SPICE Models SPICE parameters for a generic 0.5 um process, G5 (0.6 um drawn gate length). .MODEL CMOSN NMOS LEVEL=3 PHI=0.7 TOX=10E-09 XJ=0.2U TPG=1 VTO=0.65 DELTA=0.7+ LD=5E-08 KP=2E-04 UO=550 THETA=0.27 RSH=2 GAMMA=0.6 NSUB