HDB3编解码.doc

hdb3编解码的解码源程序（完整版）?? 2009-05-19 07:32:30|??分类：?默认分类|举报|字号?订阅 library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity decode is?port(codein: in std_logic_vector(1 downto 0);????? clk,reset: in std_logic;???? codeout: out STD_LOGIC);end decode;architecture rtl of decode is? signal reg0,reg1: std_logic_vector(4 downto 0);? signal mm: std_logic_vector(1 downto 0);??begin??process(clk,codein)begin???? if(clkevent and clk=1)then??????? reg1(4)=codein(1);????? reg0(4)=codein(0);???????????? reg1(3 downto 0)=reg1(4 downto 1);????? reg0(3 downto 0)=reg0(4 downto 1);???????????? if codein(0)=1 and codein(1)=0 and reg0(4 downto 1)=0001 and reg1(4 downto 1)=0000 then???????????????? reg0=00001;???????????????? reg1=00000;????????????? elsif codein(0)=0 and codein(1)=1 and reg0(4 downto 1)=0000 and reg1(4 downto 1)=0001 then???????????????? reg0=00001;???????????????? reg1=00000;????????????? elsif codein(0)=1 and codein(1)=0 and reg0(4 downto 2)=001 and reg1(4 downto 2)=000 then???????????????? reg0=0000 reg0(1);???????????????? reg1=0000 reg1(1);????????????? elsif codein(0)=0 and codein(1)=1 and reg0(4 downto 2)=000 and reg1(4 downto 2)=001 then???????????????? reg0=0000 reg0(1);???????????????? reg1=0000 reg1(1);???????????????? else????????????????? reg0=codein(0) reg0(4 downto 1);???????????????? reg1=codein(1) reg1(4 downto 1);????????????? end if;?????????? end if;?? end process;? process(clk,reset)begin??????? if(reset=1)then???????? codeout=0;????????? elsif (reg0(0)=1 AND reg1(0)=0)OR(REG0(0)=0 AND REG1(0)=1) then???????????????? codeout=1;?????????????? else????????????????? codeout=0;?????????????? end if;????????????? end process;?END RTL;l hdb3编解码的源程序（完整版）?? 2009-05-19 07:34:41|??分类：?默认分类|举报|字号?订阅 ?library ieee;?use ieee.std_logic_1164.all;??entity hdb3 is?port(codein: in std_logic;??????? clk?? : in std_logic;????? clr?? : in std_logic;?????????????? --复位信号????? codeout: out std