8-new.ppt

西安理工大学 微电子学硕士课程 第8章 动态逻辑电路 动态四输入与非门 四、动态逻辑电路存在的问题-1:电荷泄漏 泄漏电荷的影响 电荷泄漏的解决方法 解决方法:对中间节点也进行预充电 时钟馈通 动态逻辑门的级联问题 多米诺逻辑 为什么称做多米诺? np-CMOS (Zipper) 如何选择逻辑方式 设计的简易程度，鲁棒性，面积，速度，功耗 作业： leakage sources are reverse-biased diode (1) and the sub-threshold leakage (2) of the NMOS pulldown device. Charge stored on CL will leak away with time (input in low state during evaluation) Requires a minimum clock rate - so not good for low performance products such as watches (or when have conditional clocks) PMOS precharge device also contributes some leakage due to reverse bias diode (3) and subthreshold conduction (4) that, to some extent, offsets the leakage due to the pull down paths. During precharge, Out is VDD and inverter out is GND, so keeper is on During evaluation if PDN is off, the keeper compensates for drained charge due to leakage. If PDN is on, there is a fight between the PDN and the PUN - circuit is ratioed so PDN wins, eventually Note Psc during switching period when PDN and keeper are both on simultaneously CA initially discharged and CL fully charged. Danger is that signal levels can rise enough above VDD that the normally reverse-biased junction diodes become forward-biased causing electrons to be injected into the substrate. Out2 should remain at VDD since Out1 transitions to 0 during evaluation. However, since there is a finite propagation delay for the input to discharge Out1 to GND, the second output also starts to discharge. The second dynamic inverter turns off (PDN) when Out1 reaches VTn. Setting all inputs of the second gate to 0 during precharge will fix it. Correct operation is guaranteed (ignoring charge redistribution and leakage) as long as the inputs can only make a single 0 - 1 transition during the evaluation period * * 半导体 集成电路 基本电路的工作原理 动态逻辑电路的优缺点 动态逻辑电路中存在的问题及解决方法 多米诺逻辑 内容提要 CMOS静态逻辑电路 p n A O 逻辑门的设计 O A B A A A B B B 输入信号加在栅极上，而输出电压从漏极输出 输出为低电平逻辑时，NMOS网 工作 输出为高电平逻辑时，PMOS 网工作 O p A n p B n 优点：低功耗 缺点：随着逻辑的复杂性增加，晶体管成倍增加 知识点复习-1 P网 N网