有限状态机(ASM)(FSM).pptVIP

Chapter 4 DESIGN FOR FINITE STATE MACHINES(FSM)(OR ASM) Sequential circuits are also called finite state machines (FSMs), which is a more formal name that is often found in technical literature. The name derives from the fact that the function behavior of these circuits can be represented using a finite number of states. 一般有限状态机结构框图 我们知道，任何数字系统都可以分为相互作用的控制单元（control unit）和数据通道（data path）两部分。数据通道通常由组合逻辑构成，而控制单元通常由时序逻辑构成，任何时序电路都可以表示为有限状态机（Finite State Machine，FSM）。本章主要介绍有限状态机实现复杂时序逻辑电路的设计。 数字系统控制部分的每一个部分都可以看作一种状态，与每一控制相关的转换条件指定了状态的下一个状态和输出。根据有限状态机的输出与当前状态和当前输入的关系，可以将有限状态机分成Moore型有限状态机和Mealy型有限状态机两种。从现实的角度，这两种状态机都可以实现同样的功能，但是它们的时序不同， 在图中描述了Moore型有限状态机的示意图 与Moore型有限状态机不同，Mealy型有限状态机的输出不单与当前状态有关，而且还与输入信号的当前值有关。下图描述了Mealy型有限状态机的示意图。 For Example 1: Design a modulo-5 counter. 1.The first step in designing a FSM is to determine how many states are needed and which transitions are possible from one state to another. S0 S1 S4 S3 S2 /0 /0 /0 /0 /1 Figure 4.1 State diagram 2. State Assignment The state diagram in Figure 4.1 defines the five state in terms of letters S0,S1,S2,S3,S4. When implemented in a logic circuit, each state is represented by a particular valuation (combination of values) of state variables. Each state variable may be implemented in the form of a flip-flop. Present state y2y1y0 Next state y2y1y0 Output cout S0: 000 S1: 001 S2: 010 S3: 011 S4: 100 000 001 010 011 100 000 001 0 0 0 0 1 0 Figure 4.2 State-assigned table library ieee; use ieee.std_logic_1164.all; entity state_cn5 is port(clk: in std_logic; y: out std_logic_vector(2 downto 0); cout: out std_logic); end state_cn5; architecture rtl of state_cn5 is type state is (s0,s1,s2,s3,s4); signal presentstate, nextstate: state; begin switch_to_nextstate:process(clk) --主控时序进程 begin if clkevent and clk=1 then presentstate=nextstate; end if; end process switch_to_nextstate; change_state_mode: process(presentstate)-