(word)ADI ADuCRF101低功耗无线数据采集解决方案.docxVIP

(word)ADI ADuCRF101低功耗无线数据采集解决方案.docx

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(word)ADI ADuCRF101低功耗无线数据采集解决方案

ADI ADuCRF101低功耗无线数据采集解决方案关键字:工业控制, 数据采集ADI公司的ADuCRF101是全集成无线数据采集系统,集成了12位SAR ADC,低功耗ARM Cortex?-M3处理器, 862 MHz- 928 MHz 和431 MHz- 464 MHz RF收发器以及闪存/EE存储器,包括UART, I2C, SPI, GPIO端口和PWM在内的外设,主要用在无线传感器,远程医疗系统,工业和家庭自动化,财产跟踪,安全系统以及医疗保健设备等.本文介绍了ADuCRF101主要特性和优势,框图, ADuCRF101迷你评估板主要特性,电路图和PCB元件布局图.The ADuCRF101 is a fully integrated, data acquisition solution that is designed for low power, wireless applications. It features a 12-bit analog-to-digital converter (ADC), a low power ARM Cortex?-M3 processor, a 862 MHz to 928 MHz and 431 MHz to 464 MHz RF transceiver, and Flash?/EE memory. The ADuCRF101 is packaged in a 9 mm × 9 mm LFCSP.The data acquisition section consists of a 12-bit SAR ADC. The six inputs can be configured in single-ended or differential mode. When configured in single-ended mode, they can be used for ratiometric measurements on sensors that are powered, when required, from the internal low dropout regulator (LDO). An internal battery monitor channel and an on-chip tempera-ture sensor are also available.This wireless data acquisition system is designed to operate in battery-powered applications where low power is critical. The device can be configured in normal operating mode or different low power modes under direct program control. In flexi mode, any peripheral can wake up the device and operate it. In hibernate mode, the internal wake-up timer remains active. In shutdown mode, only an external interrupt can wake up the device.The ADuCRF101 integrates a low power ARM Cortex-M3 processor. It is a 32-bit RISC machine, offering up to 1.25 DMIPS peak performance. The ARM Cortex-M3 processor also has a flexible 14-channel direct memory access (DMA) controller that supports communication peripherals, serial peripheral interface (SPI), UART, and I2C. Also provided on chip are 128 kB of nonvolatile Flash/EE memory and 16 kB of SRAM.A 16 MHz on-chip oscillator generates the system clock. This clock can be internally divided for the processor to operate at a lowe

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