FPGA13.pptVIP

可编程I/O 接口电平： 3.3 LVTTL ,VCC3.3V VIh=2V,VIL=0.8V,VOH=2.4V,VOL=0.8V. 2.5 LVTTL ,VCC3.3V VIh=1.7V,VIL=0.7V,VOH=2V,VOL=0.2V. 3.3V LVCMOS VCC3.3V VIh=2V,VIL=0.7V,VOH=3.2V,VOL=0.1V. LVDS Low Voltage Differential Signaling ALtera Stratix V 的特性 动态重新配置 The ADCs in the XADC block are fast and precise. These can replace external ADCs in many applications, reducing overall system cost. This can be especially true in systems built using smaller Artix-7 devices. The XADC can generate alarm outputs whenever one of the internal measurements goes outside bounds set in the control registers. 2013204146 张聪 * SPR 综合、布局、布线。 * 为了克服PAL器件灵活性差的缺点， 可以提供不同或阵列大小和不同管脚数的器件。 PAL对后来的可编程器件的发展影响很大 * The addition of a flip-flop and multiplexer allows implementation of both combinational and sequential logic. MUX selects combinational or sequential logic The output can be feed back into AND plane to be used as input to other cells. This allows the implementation of circuits that have multiple stages of logic gates and registers. * Basic PLDs can only implement designs of fairly modest sizes. The basic concept of a CPLD is many PLD blocks resident in one device with a high level of programmable connectivity * It is possible that some masters and slaves will use different clock domains, indicated as colored regions on this slide, and then the system will need some means to cross clock domains in a metastability-hardened way. It is possible that some masters and slaves will use different clock domains, indicated as colored regions on this slide, and then the system will need some means to cross clock domains in a metastability-hardened way. * 每个LAB包含8个自适应逻辑模块 * 需要更高的电压才能导通 * Actel ，20世纪80~90年代，大多数芯片上的逻辑门不超过5万个，设计周期可用几周或几个月来衡量，因此设计门阵列可节省2~3周的时间对于整个设计周期来讲是相当可观的足以补偿芯片尺寸增加带来的不利之处。但随着深亚微米工艺的出现，集成度的提高，所需设计时间显著增加，设计生产周期的少量缩短不再很重要，此外金属连线已成为集成电路制造过程中最费事，最影响成品率的部分，门阵列的一些优势已经越来越小 1994年由国家半导体公司引进。LVDS是采用差动的传输方式，电压输出与接收端需要100欧姆的终端阻抗（Terminating Resistor）。LVDS允许采用点对点（Point-to-Point）与分支（Multi-Drop）的连接方式。实现差动信号