AlteraCycloneVSoCFPGA系列开发方案.docxVIP

Altera Cyclone V SoC FPGA 系列开发方案时间：2016-08-05 12:02:30?????? 作者：Altera?????? 来源：中电网Altera公司的Cyclone V SoC FPGA 系列基于28nm低功耗(LP)工艺,提供需要5G收发器应用的最低功耗,和以前的产品检验相比,功耗降低40%.器件集成了基于ARM处理器的硬件处理器系统(HPS),具有更有效的逻辑综合功能,收发器系列和SoC FPGA系列,从而降低系统功耗,成本和产品上市时间,主要用在工业,无线和有线通信,军用设备和汽车市场.本文介绍了Cyclone V SoC FPGA 系列主要优势和特性,架构图,HPS特性以及Cyclone V SX SoC开发板主要特性,框图和电路图.Altera’s Cyclone??V FPGAs provide the industry’s lowest system cost and power, along with performance levels that make the device family ideal for differentiating your high-volume applications. You’ll get up to 40 percent lower total power compared with the previous generation, efficient logic integration capabilities, integrated transceiver variants, and SoC FPGA variants with an ARM?-based hard processor system (HPS).The Cyclone??V devices are designed to simultaneously accommodate the shrinking power consumption, cost, and time-to-market requirements; and the increasing bandwidth requirements for high-volume and cost-sensitive applications.?Enhanced with integrated transceivers and hard memory controllers, the Cyclone??V devices are suitable for applications in the industrial, wireless and wireline, military, and automotive markets.?Built on the 28-nm low power (LP) process technology, Altera’s Cyclone V FPGAs deliver the lowest power solution for applications requiring up to 5G transceivers. Compared to previous generations, Cyclone V FPGAs offer a 40-percent power reduction, with a balance of power reduction from all areas. ?图1.Cyclone V SoC FPGA架构图图2.Cyclone V SoC框图硬件处理器系统(HPS)特性:925 MHz, dual-core ARM??Cortex?-A9 MPCore? processorEach processor core includes:32 KB of L1 instruction cache, 32 KB of L1 data cacheSingle- and double-precision floating-point unit and NEONTM?media engineCoreSightTM?debug and trace technology512 KB of shared L2 cache64 KB of scratch RAMMultiport SDRAM controller with support for DDR2, DDR3, and LPDDR2 and optional error correction code (ECC) support8-channel direct memory access (DMA) controllerQS