[Chapter 5 Hardware Description Languages].pptVIP

Chapter5 Hardware Description Languages (硬件描述语言) QuatusII原理图设计 掌握：学习使用QuatusII 工具，利用图形法和波形法进行数字逻辑电路仿真 Outline What Why HDL? Verilog HDL 模块的概念与结构 标识符、数的表示、数的类型 运算符号 Abstraction Levels Gates Dataflow Procedural Examples What Why HDL? Hardware Description Language(HDL) A software programming language used to model the intended operation of a piece of hardware Why HDL? Text-based design rather than Schematic design ASIC complexity increase faster time-to-market Simulation Logic Synthesis Words are better than pictures PLD, CPLD and FPGA became inexpensive and commonplace What is need for Hardware Description Language? Model, Represent, And Simulate Digital Hardware Hardware Concurrency Parallel Activity Flow Semantics for Signal Value And Time Special Constructs And Semantics Edge Transitions Propagation Delays Timing Checks History of HDL First HDL PALASM, 1980s--Logic equation Then more complex (minimization, if-then-else statement) CUPL (Complier Universal for Programmable Logic) ABEL (Advanced Boolean Equation Language) Verilog HDL VHDL represents another high level language for digital system design. VHDL = VHSIC HDL VHSIC = Very High Speed Integrated Circuit HDLs Software: Assembler ?high-level language, like C, C++, Java Hardware: block diagram schematic ?HDL Efficient ?Large, complex, abstraction HDL Tool Suits Text editor Complier Synthesizer Simulator Template generator Schematic viewer Translator Timing analyzer Back annotator Design flow Introduction to Verilog HDL Originally designed in 1983/1984 as a proprietary verification /simulation IEEE standard 1364 in 1995 Similar to C language 4 value logic (0, 1, x, z) HDL which provides a wide range of levels of abstraction Architectural, Algorithmic, RTL, Gate, Switch Mixed level modeling and simulation Description of digital systems only Interactive usage Hierarchical specification History 1981 Gateway Design Automation was founded Phil Mooby make GHDL(GenRad’s HDL) and HILO simulator 1983 Gateway re