计算机组成原理验报告2013.docVIP

实验名称：QuartusII与硬件描述语言应用 指导教师： 实验日期： 2013年 月 日 实验地点： 成绩： 实验目的实验 1、利用QuartusII完成原理图输入设计逻辑关系原理图。 2、利用VHDL语言完成简单逻辑关系描述逻辑关系。 3、利用VHDL语言实现全加器的语言描述（选做）实验目的 1计数和重装计数器初值计数的实现方法。 3、掌握地址寄存其从程序计数器获得数据和从内部总线获得数据的实现方法。 实验 1. 按照图程序计数器原理图编辑、输入电路。对输入原理图进行编译、引脚锁定、仿真。 2. 通过B[7..0]设置程序计数器的预加载数据。当LDPC=0时，观察程序计数器自动加1的功能；当LDPC=1时，观察程序计数器加载输出情况。 3、分别观察当LDAR=0时和LDAR=1时，地址寄存器AR的输入和输出情况。 利用实验设备，根据数据通路实现地址切换来获取内存不同性质的数据。 图 程序计数器原理图 实验步骤： 实验总结： 实验评价（教师）： section of the Department of project management; Project documents and information: Project Engineering Department; Materials and equipment: material supply projects; Security controls: the project Department of safety and security; Construction machinery: Project Engineering Department; Financial: Project Management Department of finance; Security and fire services: project security. 3.3.5 management representative and project manager in this item specifies that the Chief Engineer is the management representative, responsible for the operation of quality management system and supervision, regardless of how his other responsibilities, should have a clear mandate to: ensure that the quality management system is implemented and maintained; The running of the quality management system to the project manager, including needed improvements; Always be aware that the customers needs and requirements. 3.4 3.4.1 project management review should be an annual review of its quality management system to ensure its continuing suitability, adequacy and effectiveness. 3.4.2 Administration review by the proj