System Verilog.pptVIP

System Verilog Extensive enhancements to the IEEE 1364 Verilog-2001 standard. By Accellera More abstraction: modeling hardware at the RTL and system level Verification Improved productivity, readability, and reusability of Verilog based code Enhanced IP protection Motivation As design sizes have increased: Design Code size verification code size Simulation time Have increased as well. Co-design Higher Level Design, simulation, synthesis, Test… Alternatives SystemC model full systems at a much higher level of abstraction Hardware Verification Languages (HVLs) Verisitys e Synopsys Vera