vlsi circuit design 09 adders.pptVIP

Adder Design Review: Basic Building Blocks Datapath Execution units Adder, multiplier, divider, shifter, etc. Register file and pipeline registers Multiplexers, decoders Control Finite state machines (PLA, ROM, random logic) Interconnect Switches, arbiters, buses Memory Caches (SRAMs), TLBs, DRAMs, buffers The 1-bit Binary Adder S = A ? B ? Cin Cout = AB | ACin | BCin (majority function) FA Gate Level Implementations Static CMOS Adder Mirror Adder Mirror Adder Features The NMOS and PMOS chains are completely symmetrical with a maximum of two series transistors in the carry circuitry, guaranteeing identical rise and fall transitions if the NMOS and PMOS devices are properly sized. When laying out the cell, the most critical issue is the minimization of the capacitances at node !Cout (four diffusion capacitances, two internal gate capacitances, and two inverter gate capacitances). Shared diffusions can reduce the stack node capacitances. The transistors connected to Cin are placed closest to the output. Only the transistors in the carry stage have to be optimized for optimal speed. All transistors in the sum stage can be minimal size. XOR FA CPL FA A 64-bit Adder/Subtractor Ripple Carry Adder (RCA) Inversion Property Exploiting the Inversion Property Fast Carry Chain Design The key to fast addition is a low latency carry network What matters is whether in a given position a carry is generated Gi = Ai Bi = AiBi propagated Pi = Ai ? Bi (sometimes use Ai | Bi) annihilated (killed) Ki = !Ai !Bi Giving a carry recurrence of Ci+1 = Gi | PiCi Fast Carry Chain Design The key to fast addition is a low latency carry network What matters is whether in a given position a carry is generated Gi = Ai Bi = AiBi propagated Pi = Ai ? Bi (sometimes use Ai | Bi) annihilated (killed) Ki = !Ai !Bi Giving a carry recurrence of Ci+1 = Gi | PiCi Manchester Carry Chain Switches controlled by Gi and Pi Total delay of time to form the switch control s