第二讲：DSP体系结构和汇编语言1new.pptVIP

VLIW特点 VLIW architectures rely on compile-time detection of parallelism → the compiler analysis the program and detects operations to be executed in parallel;such operations are packed into one “large”instruction. After one instruction has been fetched all the corresponding operations are issued in parallel. No hardware is needed for run-time detection of parallelism. The window of execution problem is solved: the compiler can potentially analyse the whole program in order to detect parallel operations. C6000芯片特点(1) 定点/浮点系列兼容DSP，CPU主频100～600MHz~1.1GHz VelociTI? 先进VLIW结构内核 8个独立的功能单元：6个ALU（32/4