飞思卡尔后背资料6课程.pptVIP

Analog to Digital Converter A/D RegisterMap A/D Clock Select/ Prescaler Conversion Timing A/D Control Registers (Cont’d) Result Registers SCF - Sequence Complete Flag - Set at end of conversion sequence in single conversion mode (SCAN = 0) and at the end of first conversion sequence in continuous conversion mode (SCAN = 1). - A write to this register clears SCF flag when (AFFC = 0). ETORF - External Trigger Overrun Flag -Sets if active edges occur while conversion sequence in progress. FIFOR - Sets when the Result Register has been written before it was read by the CPU ( CCF w