vhdl基本语素语法语句(杨).ppt

* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * S0 S2 0/0 1/0 S1 1/0 0/1 0/0 1/0 Mealy型序列信号检测器—状态图 序列信号：110 S x/Z ‘1’ ‘11’ S0/0 S2/0 0 1 S1/0 1 0 1 Moore型序列信号检测器—状态图 序列信号：110 S/Z x ‘1’ ‘11’ S3/1 ‘110’ 0 0 1 LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY sqs IS PORT( x,clk: in Std_logic; z: out Std_logic); END sqs; Mealy型-VHDL代码转换 ARCHITECTURE a OF mealy IS TYPE STATE_TYPE IS (s0, s1, s2); SIGNAL state: STATE_TYPE; BEGIN Mealy型-VHDL代码