超大CMOS集成电路原理Chapter12.ppt

Digital Integrated CircuitsA Design Perspective Chapter Overview Semiconductor Memory Classification Memory Timing: Definitions Memory Architecture: Decoders Array-Structured Memory Architecture Hierarchical Memory Architecture Block Diagram of 4 Mbit SRAM Contents-Addressable Memory Memory Timing: Approaches Read-Only Memory Cells MOS OR ROM MOS NOR ROM MOS NOR ROM Layout MOS NOR ROM Layout MOS NAND ROM MOS NAND ROM Layout NAND ROM Layout Equivalent Transient Model for MOS NOR ROM Word line parasitics Wire capacitance and gate capacitance Wire resistance (polysilicon) Bit line parasitics Resistance not dominant (metal) Drain and Gate-Drain capacitance Equivalent Transient Model for MOS NAND ROM Decreasing Word Line Delay Precharged MOS NOR ROM Non-Volatile MemoriesThe Floating-gate transistor (FAMOS) Floating-Gate Transistor Programming A “Programmable-Threshold” Transistor FLOTOX EEPROM EEPROM Cell Flash EEPROM Cross-sections of NVM cells Basic Operations in a NOR Flash Memory―Erase Basic Operations in a NOR Flash Memory―Write Basic Operations in a NOR Flash Memory―Read NAND Flash Memory NAND Flash Memory Characteristics of State-of-the-art NVM Read-Write Memories (RAM) 6-transistor CMOS SRAM Cell CMOS SRAM Analysis (Read) CMOS SRAM Analysis (Read) CMOS SRAM Analysis (Write) CMOS SRAM Analysis (Write) 6T-SRAM — Layout Resistance-load SRAM Cell SRAM Characteristics 3-Transistor DRAM Cell 3T-DRAM — Layout 1-Transistor DRAM Cell DRAM Cell Observations Sense Amp Operation 1-T DRAM Cell SEM of poly-diffusion capacitor 1T-DRAM Advanced 1T DRAM Cells Static CAM Memory Cell CAM in Cache Memory Periphery Row Decoders Hierarchical Decoders Dynamic Decoders 4-input pass-transistor based column decoder 4-to-1 tree based column decoder Decoder for circular shift-register Sense Amplifiers Differential Sense Amplifier Differential Sensing ― SRAM Latch-Based Sense Amplifier (DRAM) Charge-Redistribution Amplifier Charge-Redistribution Amplifier―EPROM Single-to-Differentia