WarpProcessorsTowardsSeparatingFunctionandArchitect.pptVIP

Lysecky, R. test Warp ProcessorsTowards Separating Function and Architecture Frank Vahid Professor Department of Computer Science and Engineering University of California, Riverside Faculty member, Center for Embedded Computer Systems, UC Irvine Warp Processor Ph.D. students: Roman Lysecky (Ph.D. 2004), Greg Stitt (Ph.D. 2005) This research is supported in part by the National Science Foundation, the Semiconductor Research Corporation, and Motorola Main IdeaWarp Processors – Dynamic HW/SW Partitioning FPGAs are Programmable FPGA do Bit Manipulation Fast 64 instructions 32 to 128 cycles FPGAs Support Much Parallelism 1000’s of instructions Several thousand cycles Why aren’t FPGAs Part of Mainstream Computing? Benefits known for over a decade Hardware/software partitioning research since early 90s PRISM [Athanas, Silverman]; TOSCA [Balboni, Fornaciari, Sciuto]; COSYMA [Henkel/Ernst]; Vulcan [Gupta/DeMicheli]; SpecSyn [Gajski/Vahid/Narayan/Gong]; etc. Microprocessor/FPGA architectures research since early 90s DISC [Wirthlin, Hutchings]; GARP [Hauser, Wawrzynek]; Chimaera [Hauck, Fry, Hosler, Kao]; Morphosys [Lee, Singh, Lu, et al] Commercial ventures for several years Chameleon Morphotec Stretch [] using Tensilica [] (April 2004) New Atmel, Triscend, Altera, Xilinx devices in past few years… Single-Chip Microprocessor/FPGA Platforms Appearing Commercially Why Aren’t FPGAs Mainstream? Doesn’t fit well with SW Well-established languages, tools and flows Concept of a standard binary is missing in FPGA world Thus, FPGAs limited to CAD domain But for every 1 CAD user -- 100 software writers Only about 15,000 CAD seats worldwide; millions of compiler seats Standard Binary is Important Separates function from architecture Tools and architectures can be developed independently Can even dynamically translate/optimize UQBT [Cifuentes]; Dynamo [Bala, Duesterwald, Banerjia] Transmeta Crusoe, Efficeon [] and modern Pentiums Java bytecode Partial Solution to Bring FP