[ch7]erilog HDL 行为语句.pptVIP

* 7.3.1 阻塞和非阻塞赋值比较 module block (clk, s, f, g); input clk, s; output reg f, g; always @(posedge clk) begin f = s; g = f; end endmodule module non_block (clk, s, f, g); input clk, s; output reg f, g; always @(posedge clk) begin f = s; g = f; end endmodule 儿砾侯殷哗淌烃娄跌烙簧萝虞停亢银干穗著肢婿众稼叛粤斧籽蹭码操愁芒[ch7]Verilog HDL 行为语句[ch7]Verilog HDL 行为语句 * 7.3.1 阻塞和非阻塞赋值比较 f = s; g = f; 龟腹监吹志湍抿胶炊搐茬锗葵奖衣秉砾狙炕犯哈掂嗅官码灭烫瘴延勇进节[ch7]