《天津市科技统计年鉴》编辑部title.pptVIP

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  • 约1.82万字
  • 约 67页
  • 2016-12-21 发布于广东
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Computer Systems Research at UNT More CPU’s per chip -- Multi-core systems More threads per core -- hyper-threading More cache and cache levels (L1, L2, L3) System on a chip and Network on chip Hybrid system including reconfigurable logic We propose innovative architecture that “scales” in performance as needed, but disables hardware elements when not needed. We address several processor elements for performance and energy savings Computer Architecture Research Computer Architecture Research Computer Architecture Research Computer Architecture Research Computer Architecture Research Overview o

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