译码器的VDL设.docVIP

实验名称： 译码器的VHDL设计 二、用WHEN_ELSE语句编写具有使能端的3-8译码器 1.实体框图 2.程序设计 ①编译前的程序 Entity Dec38A is port(s1,s2,s3:in bit; A2,A1,A0:in bit; Y:out bit_vector(7 downto 0)); End Dec38A; Architecture two of Dec38A is Begin Y when s1s2s3=100 and A2A1A0=000 else when s1s2s3=100 and A2A1A0=001 else when s1s2s3=100 and A2A1A0=010 else when s1s2s3=100 and A2A1A0=011 else when s1s2s3=100 and A2A1A0=100 else when s1s2s3=100 and A2A1A0=101 else when s1s2s3=100 and A2A1A0=110 else when s1s2s3=100 and A2A1A0=111 else ; End architecture two; ②程序编译错误情况 错误1： Error (10482): VHDL error at Dec38A.vhd(15): object s1s2s3 is used but not declared 错误2： Error (10482): VHDL error at Dec38A.vhd(15): object A2A1A0 is used but not declared ③正确的程序 Entity Dec38A is port(s1,s2,s3:in bit; A2,A1,A0:in bit; Y:out bit_vector(7 downto 0)); End Dec38A; Architecture two of Dec38A is signal s:bit_vector(1 to 3); signal A:bit_vector(2 downto 0); Begin s=s1 s2 s3; A=A2 A1 A0; Y when s=100 and A=000 else when s=100 and A=001 else when s=100 and A=010 else when s=100 and A=011 else when s=100 and A=100 else when s=100 and A=101 else when s=100 and A=110 else when s=100 and A=111 else ; End architecture two; 3.仿真波形图 4.仿真波形分析 S1、S2、S3是使能端，A0、A1、A2是选通端，Y7~Y0是输出端 当S1、S2、S3为100时，译码器工作 A=000时， YA=001时，Y=A=010时，YA=011时，YA=100时，YA=101时，Y=A=110时，YA=111时，Y=；使能端无效时 ; 二、用WHEN_ELSE语句实现驱动共阳极数码管七段显示译码器 1.实体框图 2.程序设计 ①编译前的程序 Library ieee; Use ieee.std_logic