vhdl的数字钟.docVIP

基于vhdl的数字钟设计 1、主控模块电路图 主控模块代码： library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity control is port(clk,k,set,reset,trans : in std_logic; jh,jm,js,nh,nm,ns,flashh,flashm,flashs,selct :out std_logic); end control; architecture behav of control is type states is(s0,s1,s2,s3,s4,s5,s6,s7); signal current_state,next_state :states; begin process (reset,clk,next_state,current_state,k,set) begin if (reset=1)then current_state=s0; elsif(clkevent and clk=1)then current_state=next_state; end if; case current_state is when s0= flashh=0;flashm=0;flashs=0;jh=0;jm=0;js=0; nh=0;nm=0;ns=0;selct=1; if(trans=1)then next_state=s4; elsif(set=1 ) then next_state=s1; else next_state=s0; end if; when s1= flashh=1;flashm=0;flashs=0;jh=1;jm=0;js=0; nh=0;nm=0;ns=0;selct=1; if (set=1)then next_state=s2; else next_state=s1; end if; when s2= flashh=0;flashm=1;flashs=0;jh=0;jm=1;js=0; nh=0;nm=0;ns=0;selct=1; if (set=1) then next_state=s3; else next_state=s2; end if; when s3= flashh=0;flashm=0;flashs=1;jh=0;jm=0;js=1; nh=0;nm=0;ns=0;selct=1; if ( set=1 ) then next_state=s0; else next_state=s3; end if; when s4= flashh=0;flashm=0;flashs=0;jh=0;jm=0;js=0; nh=0;nm=0;ns=0;selct=0; if ( trans=1 ) then next_state=s0; elsif ( set=1 ) then next_state=s5; else next_state=s4; end if; when s5= flashh=1;flashm=0;flashs=0;jh=0;jm=0;js=0; nh=1;nm=0;ns=0;selct=0; if (set=1) then next_state=s6; else next_state=s5; end if; when s6= flashh=0;flashm=1;flashs=0;jh=0;jm=0;js=0; nh=0;nm=1;ns=0;selct=0; if (set=1 ) then next_state=s7; else next_state=s6; end if; when s7= flashh=0;flashm=0;flashs=1;jh=0;jm=0;js=0; nh=0;nm=0;ns=1;selct=0; If (set=1) then next_state=s4; else next_state=s7; end if; end case; end process; end behav; 主控模块仿真图 2、计时校时模块 计时校时代码 二选一 library ieee; use ieee.std_logic_1164.all; entity mux2_1 is port(d0,d1,en :in std_logic; sel :in std_logic; y :out std_logic); end