拉扎维《模拟集成电路设计》第二版课件 Ch14.pptVIP

* Linearization Techniques Another approach to linearization: “post-correction” View the amplifier as a cascade of voltage-to-current (V/I) converter and a current-to-voltage (I/V) converter If the V/I converter can be described as and the I/V converter as , then Vout is a linear function of Vin , for e.g. Figs. (a), (b), (c) * Linearization Techniques Possible to linearize differential pair further by adding local feedback Sense output voltage by means of M3 and M4 and return a proportional current to the sources of M1 and M2 Assume circuit is symmetric and I1 = … = I4 Ignoring CLM and body-effect, ID1 = I3 and ID2 = I4 regardless of the input signal * Linearization Techniques Input transistors maintain a constant VGS as Vin = Vin1 – Vin2 varies Current through RS (Isig) must be provided only by M3 and M4, we have Output voltage of this topology can be found to be Large number of devices in signal path produce significant noise Dependence of rO upon VDS in short-channel devices introduces some nonlinearity * Mismatch Nominally-identical devices suffer from finite mismatch due to uncertainties in manufacturing process Gate dimensions of MOSFETs suffer from random, microscopic variations and introduce mismatches between two transistors identically laid out MOS devices exhibit VTH mismatches since VTH is a function of doping levels in the channel and gate which vary randomly * Mismatch Study of mismatch consists of two steps: Identify and formulate the mechanisms leading to mismatch between devices Analyze the effect of device mismatches upon the performance of circuits For a MOSFET in saturation, Mismatches between μ, Cox, W, L, and VTH result in mismatches between ID’s (for a given VGS) or VGS’s (for a given ID) of two nominally-identical transistors Intuitively, as W and L increase, their relative mismatches ?W/W and ?L/L, i.e., larger devices exhibit smaller mismatches