building counters veriog example（建立专柜veriog的例子）.docVIP

Version 1.0 – David Black-Schaffer Building Counters Veriog Example There are many different ways to write code in Verilog to implement the same feature. In ee108a you should strive to make your code as easy to read and debug as possible. The counter example in the book instantiates a flip flop for storing the count, and then uses a case statement to build a mux to choose the next input to the flip flop based on the control signals. Let’s take a look at two ways to write this in Verilog. Example 1: This is the up/down counter code from the course reader: module UDL_Count1(clk, rst, up, down, load, in, out) ; parameter n = 4 ; input clk, rst, up, down, load ; input [n-1:0] in ; output [n-1:0] out ; wire [n-1:0] out ; reg [n-1:0] next ; DFF #(n) count(clk, next, out) ; always@(rst, up, down, load, in, out) begin casex({rst, up, down, load}) 4’b1xxx: next = {n{1’b0}} ; 4’b01xx: next = out + 1’b1 ; 4’b001x: next = out - 1’b1 ; 4’b0001: next = in ; default: next = out ; endcase end endmodule This code is fairly easy to read except that it concatenates all of the bits of the control (rst, up, down, load) into one signal and then does a case on them. Understanding what the 4’b001x: case is requires the reader to look at what the case statement is doing. Comments would help here, but we’d like to make it simpler. Example 2: This is the same up/down counter as the code from the course reader, but it is a lot easier to understand: module UDL_Count2(clk, rst, up, down, load, in, out) ; parameter n = 4 ; input clk, rst, up, down, load ; input [n-1:0] in ; output [n-1:0] out ; wire [n-1:0] out ; reg [n-1:0] next ; DFF #(n) count(clk, next, out) ; always@* begin if (rst) next = {n{1’b0}}; else if (load) next = in; else if (up) next = out + 1’b1; else if (down) next = out – 1’b1; else next = out; end endmodule It is immediately apparent that the else if (down) case is