《38译码器实验仿真结果图.docVIP

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY mux8_1 IS PORT(add : IN STD_LOGIC_vector(2 downto 0); i:IN STD_LOGIC_vector(0 to 7); y: OUT STD_LOGIC); END mux8_1; ARCHITECTURE behave OF mux8_1 IS --SIGNAL sel :STD_LOGIC_vector(2 DOWNTO 0); BEGIN --sel=A2 A1 A0; PROCESS(add,i) BEGIN CASE add IS WHEN 000 = y=i(0); WHEN 001 = y=i(1); WHEN 010 = y=i(2); WHEN 011 = y=i(3); WHEN 100 = y=i(4); WHEN 101 = y=i(5); WHEN 110 = y=i(6); WHEN 111 = y=i(7); WHEN others = NULL; END CASE; END PROCESS; END behave; 三八译码器 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY dec38 IS PORT (G1, G2A, G2B : IN STD_LOGIC; add : IN STD_LOGIC_vector(2 downto 0); Y : OUT STD_LOGIC_VECTOR(0 TO 7)); END dec38; ARCHITECTURE dataflow1 OF dec38 IS SIGNAL YI: STD_LOGIC_VECTOR(0 TO 7); --SIGNAL add: STD_LOGIC_VECTOR(2 DOWNTO 0); BEGIN --add = c b a; WITH add SELECT YI =WHEN 000, WHEN 001, WHEN 010, WHEN 011, WHEN 100, WHEN 101, WHEN 110, WHEN 111, WHEN OTHERS; Y = YI WHEN (G1 AND NOT G2A AND NOT G2B) =1 ELSE END dataflow1; 半加器 LIBRARY IEEE; --半加器描述(1)：布尔方程描述方法 USE IEEE.STD_LOGIC_1164.ALL; ENTITY h_adder IS PORT (a, b : IN STD_LOGIC; co, so : OUT STD_LOGIC); END ENTITY h_adder; ARCHITECTURE fh1 OF h_adder is BEGIN so = NOT(a XOR ( NOT b)) ; co = a AND b; END ARCHITECTURE fh1; 系列信号检测（密码核对器） library IEEE; --1110010序列检测 use IEEE.std_logic_1164.all; ENTITY xljc IS PORT ( din,clk,clr : IN STD_LOGIC; --串行数据输入/工作时钟/复位信号 ab :OUT STD_LOGIC_vector(3 downto 0));--输出检测结果 END ENTITY xljc; ARCHITECTURE one OF xljc IS signal q :integer range 0 to 7; signal d :STD_LOGIC_vector(6 downto 0);--七位待检测数据预置数 BEGIN d=11