东南大学Intel微处理器ch2_课件.pptVIP

* 地址 内容 19H 0CH 1AH 1FH 1BH 01H 1CH 23H 1DH 74H 1EH ABH 1FH 41H 20H 42H 21H 43H 22H 44H 23H 45H 地址为1AH的字节数据1FH 1AH 1FH 1BH 01H 1CH 23H 地址为1EH的规则字数据41ABH 1EH ABH 1FH 41H 首地址为1FH的字符串“ABCDE” 21H 43H 23H 45H 20H 42H 22H 44H 1FH 41H 地址为1AH的双字数据7423011FH； 如解释为指针数据，则段基址为7423H，偏移量为011FH 1AH 1FH 1BH 01H 1CH 23H 1DH 74H Chapter 2: The Microprocessor and  its Architecture 2–1 Internal Microprocessor Architecture 2–2 Real Mode Memory Addressing Contents Introduction programmable internal programming model how its memory space is addressed. Addressing modes. 8086 through the 80286 are fully upward-compatible to the 80386 through Core2. Figure 2–1 illustrates the programming model 8086 through Core2 microprocessor. including the 64-bit extensions 8086:16-bit The Programming Model Figure 2–1??The programming model of the 8086 through the Core2 microprocessor including the 64-bit extensions. （8086） The Programming Model Special-Purpose Registers RFLAGS segment registers include CS, DS, ES, SS IP addresses the next instruction in a section of memory. SP addresses an area of memory called the stack. Figure 2–2??The EFLAG and FLAG register counts for the entire 8086 and Pentium microprocessor family. C (carry) holds the carry after addition or borrow after subtraction: also indicates error conditions P (parity) is the count of ones in a number expressed as even or odd. Logic 0 for odd parity; logic 1 for even parity. A (auxiliary carry) holds the carry (half-carry) after addition or the borrow after subtraction between bit positions 3 and 4 of the result. Special-Purpose Registers Z (zero) shows that the result of an arithmetic or logic operation is zero. S (sign) flag holds the arithmetic sign of the result after an arithmetic or logic instruction executes. T (trap) The trap flag enables trapping through an on-chip debugging feature. I (interrupt) controls operation of the INTR (interrupt re