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Advanced PCB design and layout for EMC
Part 1 – Saving time and cost overall
By Eur Ing Keith Armstrong C.Eng MIEE MIEEE, Cherry Clough Consultants
/archive/article.asp?artid=110
This is the first in a series of eight articles on good-practice EMC design techniques for printed circuit board (PCB) design and layout. This series is intended for the designers of any electronic circuits that are to be constructed on PCBs, and of course for the PCB designers themselves. All applications areas are covered, from household appliances, commercial and industrial equipment, through automotive to aerospace and military.
These PCB techniques are helpful when it is desired to…
Save cost by reducing (or eliminating) enclosure-level shielding
Reduce time to market and compliance costs by reducing the number of design iterations
Improve the range of co-located wireless datacomms (GSM, DECT, Bluetooth, IEEE 802.11, etc.)
Use very high-speed devices, or high power digital signal processing (DSP)
Use the latest IC technologies (130nm or 90nm processes, ‘chip scale’ packages, etc.)
The topics to be covered in this series are:
Saving time and cost overall
Segregation and interface suppression
PCB-chassis bonding
Reference planes for 0V and power
Decoupling, including buried capacitance technology
Transmission lines
Routing and layer stacking, including microvia technology
A number of miscellaneous final issues
A previous series by the same author in the EMC Compliance Journal in 1999 “Design Techniques for EMC” included a section on PCB design and layout [1], but only set out to cover the most basic PCB techniques for EMC – the ones that all PCBs should follow no matter how simple their circuits. This series is posted on the web and the web versions have been substantially improved over the intervening years [2]. Other articles by this author (e.g. [3] [4]) have also addressed basic PCB techniques for EMC. This series will not repeat the basic design information in
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