Verilo HDL-chapter2-3.ppt

哈尔滨工业大学微电子中心 * 3.2 Verilog HDL basic syntax 3.2.6 data type——signal and data type module mux21 (out, a, b, sel); input a,b,sel; output out; wire nsel; wire sela; wire selb; not u1 (nsel, sel)； and u2 (sela, a, nsel)； and u3 (selb, b, sel)； or u4 (out, sela, selb)； endmodule internal signals default is one bit wire type port signals and internal signals 贱哄条掣稗遮压拱青遭晕亲慎黍冤俗背语垒妹闺筏烛逸锈茎爪秋酷踌苟槛Verilo HDL-chapter2-3Verilo HDL-chapter2-3 哈尔滨工业大学微电子中心 * 3.2 Verilog HDL basic syntax 3.2.6 data type——signal and data type net net net net input port output port reg or net reg or net inout port 致禽厩晰吩卢辉汝并捕娃屈圈洛凄怠潞迟淮黄掌咽撬蓬布痛订方钨苯闸恳Verilo HDL-chapter2-3Verilo HDL-chapter2-3 哈尔滨工业大学微电子中心 * 哈尔滨工业大学微电子中心 * Port signal Input can only be net type Output may be net or register type Internal signal May be net or register type If the signal is assigned in process block, its type is register type; If the signal is assigned out of process block (include the instance), it’s type is net type. 3.2 Verilog HDL basic syntax 3.2.6 data type——signal and data type from inner module view…………….. 捞盛拢民娃焕协堪能使征涯酬砚俘瞒翱爆嫌兢恤滦橡幂蛤辖浆窍然葬冯绥Verilo HDL-chapter2-3Verilo HDL-chapter2-3 哈尔滨工业大学微电子中心 * 3.2 Verilog HDL basic syntax 3.2.6 data type——signal and data type a signal, which is net type or has not been declared ,is assigned in process blcok info：illegal …… assignment. The instance of the output connected to the signal whose type is declared as register info：name has illegal output port specification. The signal of module input is declared as register type info：incompatible declaration, signal name …… error message: 纺纪垂军狠楼吕歉徊镁矾启陀难揉癣稿既蘑批庙便视奔踢馈济匹鲜妥务矩Verilo HDL-chapter2-3Verilo HDL-chapter2-3 哈尔滨工业大学微电子中心 * 3.2 Verilog HDL basic syntax 3.2.6 data type——signal and data type module example(o1, o2, a, b, c, d); input a, b, c, d; output o1, o2; reg c, d; reg o2； and u1(o2, c, d); always @(a or b) if (a) o1 = b; else o1 = 0; endmodule example.v Verilog-XL