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Applying full and correct constraints refers to applying constraints for all clocks in the design. Additionally, false paths and multicycle paths should be correctly constrained, as should the I/O. The timing closure flow chart was created to help achieve breakthrough performance. For additional details on synchronous design methodology, refer to the Virtex-6 and Spartan-6 HDL Coding Techniques RELs and consider attending the Essentials of FPGA Design course. Remember that while RTL code may look like software, it is really a mechanism of inferring hardware. You should always try and imagine the basic structure of the circuit that will be inferred by a particular RTL process. For example, using the + operator in RTL code will infer an adder, which will has a reasonable propagation time from the inputs to the outputs. These are just the most obvious suggestions. For every design, there may be more tricks or other clever things that can improve performance. These are the corresponding commands in XST… Timing-driven synthesis = Use Synthesis Constraints File (XCF)…Specifies an XST constraints file FSM extraction = FSM Encoding (One-Hot, Compact, Sequential, Gray, Johnson, User Specified, Speed)…Defines the coding technique used Retiming = Register Balancing…Moves registers through combinatorial logic to evenly distribute the path’s delay between register Register Duplication (same) Hierarchy Management = Keep Hierarchy Resource Sharing (same) Physical Optimization (no equivalent) Resource sharing is a technique used by synthesis tools to share operators of arithmetic functions. It decreases circuit area, which can decrease performance. The decision to move flip-flops into and out of IOBs can also be made by the MAP process during implementation. This example shows what happens when constraints are used properly. If there is no performance requirement, the tools generate a design that is as small as possible. The same is true when there are several solutions that al