ppt课件-360 n computer architecture spring2005- r a m p（360 n计算机架构spring2005 - r m p）.pptVIP

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ppt课件-360 n computer architecture spring2005- r a m p（360 n计算机架构spring2005 - r m p）.ppt

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1/17/08 RAMP Retreat Functional/Timing Split in UT FAST Derek Chiou, Dam Sunwoo, Joonsoo Kim, Nikhil Patil, William Reinhart, D. Eric Johnson, Jebediah Keefe, Hari Angepat University of Texas at Austin Electrical and Computer Engineering First, Some Terminology Host: the system on which a simulator runs Dell 390 with a single 1.8GHz Core 2 Duo and 4GB of RAM A Xilinx FPGA board Target: the system being modeled Alpha 21264 processor Dell 390 with a single 1.8GHz Core 2 Duo and 4GB of RAM FAST Goals RTL-level cycle-accuracy Complex ISA capable (x86, PowerPC) Complex micro-architecture capable (Intel Core 2) Off-the-shelf OS, apps (Windows, MS Word, Linux) Lesson I learned from my grad school career Can run other stuff too of course MP-capable (scale with FPGA resources) Fast (10MIPS range) (Relatively) easy to implement, modify, extend FAST Prototype in Real Time FAST: Speculative Functional/Timing Partitioning Proven partitioning (FastSim) FM executes instructions to completion, pushes inst trace to TM FM insts used as TM fetched insts If functional insts != timing insts, TM forces FM to rollback Eg., branch mis-speculation, resolve, memory ordering Clean inst trace/rollback interface Optimize the common case! FM runs independently from TM when functional insts == timing insts! Easy to parallelize Better target uArch simulates faster Factorized, not partitioned! (FM + TM) (monolithic simulator) FM fairly simple, only functionality TM fairly simple, only timing High Level FAST Architecture: A Parallelized Simulator Parallelized between FM TM Parallel target would have a parallelized FM, each target core conceptually running on a separate host core Parallelized TM Parallelizes nicely in hardware (FPGA) Latency tolerant, infrequent round-trips Stats can be done in hardware! (no performance impact) What Is A FAST Functional Model? Requirements Fast, Full System, generate instruction trace, support rollback Hardware functional models Fast, but FPGA impl