段成华数字集成电路第六次作业.docxVIP

数字集成系统第六次作业1.For the VHDL model given below (Code List One), compare the FIFOs implementations on CPLD and FPGA.Synthesize and verify (simulate) the VHDL design of the FIFOs;For CPLD implementation (fit) of the FIFOs, how many MCs (macrocells) and PTs (product terms) are needed? Which parameter is critical to the maximum internal clock working frequency? Try to find out this critical parameter and its corresponding circuit path.For FPGA implementation (place and route) of the FIFOs, how many LBs (logic blocks)? Which parameter is critical to the maximum internal clock working frequency? Try to find out this critical parameter and its corresponding circuit path.Try to synthesize again the design with timing constraints and compare with its former counterparts. You will create the timing constraint file by yourself and add it to your project. Please refer to the following graphic interface of ISE:2. For the VHDL model given below (Code List Two), there may be some design errors in it. Some warning(s) and/or error(s) information may be issued when synthesizing it. Try to find out such design errors and correct them.根据段老师题目中提供的程序代码，并对此书写testbench,（1）综合后的RTL schematic和功能仿真后的结果分别如下图1和图2所示。图1RTL schematic图2仿真结果(功能仿真)（2）设置芯片为XC9500 CPLDS系XC95108-7-PQ160，速度为-7，综合后报告分析如下图3 CPLD综合报告由图3可以知道，对于本程序，一共使用了87个Macrocells，占总数的百分之八十一，使用了228个Pterms，占总数的百分之四十三，资源相对充裕，满足程序的设计要求。图4 CPLD时间报告由图4可知，时钟的最小周期为15ns，受clock to setup delay影响最大，故关键路径为tcyc。延时为15ns，时钟的工作频率为66.67MHz。(3)更换芯片型号为Spartan3-xc3s200-5pq208,速度为-5，其综合报告如下图5 FPGA综合报告查Spartan3的datasheet如下图6 Spartan3 datasheet由上图知，对于选择的器件，其logic cell为4320,CLB 有24X20=480个，每个CLB包含4个slice,而对于我们的程序，一共使用了66个slice，占总数的百分之三（总slice共计1920个），故使用的CLB数为66/4=16.5,即使用了17个CLB图7时间报告关键路径为clock to setup delay，延时为4.821ns，它对时钟的工作频率影响最大。时钟的工作频率为207.42MHz。（4）图8 timing constrain图9没有设置时序约束时的报告图10设置clk周期约束为5ns时的报告图11设置clk周期约束为4.5ns时的报告图12设置clk周期约束为4ns时的报告图13设置clk周期约束为3.5ns时的报告由图10至13可以看到，当对CLK进行约束时，会对系统性能有所影响，随着条件的苛刻，best case achievable也越来越小，但当限制小到一定程度时，EDA工具可能会无法布通，