VHDL语法应用.ppt

13、VHDL语言的库文件 library IEEE; use IEEE.numeric_bit.all; entity Adder4_v2 is port(A, B: in unsigned(3 downto 0); Ci: in bit; -- 输入 S: out unsigned(3 downto 0); Co: out bit); -- 输出 end Adder4_v2; architecture overload of Adder4_v2 is signal Sum5: unsigned(4 downto 0); begin Sum5 = 0 A + B + unsigned(0=Ci); -- 加法器 S = Sum5(3 downto 0); Co = Sum5(4); end overload; 无符号矢量4位加法器的VHDL程序 卞裹拌尽滓寨肛知撬芦绝郧浓跌旅孕度赎犊怀拙躇佣肄田枫靠芦酗柳缮袍VHDL语法应用VHDL语法应用 13、VHDL语言的库文件 library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity Adder4_v3 is port(A, B: in std_logic_vector(3 dow