02_使用QuartusIITimequest时序分析器约束分析设计.ppt

Reference Documents Quartus II Handbook, Volume 3, Chapter 7 The Quartus II TimeQuest Timing Analyzer /literature/hb/qts/qts_qii53018.pdf Quick Start Tutorial /literature/hb/qts/ug_tq_tutorial.pdf Cookbook /literature/manual/mnl_timequest_cookbook.pdf Reference Documents SDC and TimeQuest API Reference Manual /literature/manual/mnl_sdctmq.pdf AN 481: Applying Multicycle Exceptions in the TimeQuest Timing Analyzer /literature/an/an481.pdf AN 433: Constraining and Analyzing Source-Synchronous Interfaces /literature/an/an433.pdf * * * * * * * * * * * * * * * * * * * * * * The TimeQuest timing analyzer tool enables Quartus II users to perform a thorough and sophisticated static timing analysis of high-performance FPGA designs. TimeQuest timing analyzer delivers many benefits to the Quartus II software user. Native SDC support - Enables users to adopt a powerful industry-standard timing analysis methodology and to achieve a higher degree of productivity due to the use (and re-use) of SDC, TCL-based scripts. Fast on-demand and interactive data reporting - Saves designers’ time, and enables users to request more detailed timing analysis only on the paths of interest. TimeQuest’s fast on-demand data reporting is complemented by a powerful GUI that reports the timing analysis data in an intuitive, easy to understand graphical format, further enhancing the users’ productivity. Small memory footprint - Enables design teams to maximize their investment in 32bits architecture computer resources as the densities of FPGAs increase. TimeQuest timing analyzer has the built-in controls necessary to automatically account for on-chip variation, and to account for rise/fall timing characteristics. * * * * This section is provided as a quick review. The idea is that the students have already attended the Quartus II training showing how to use TimeQuest. If they have not, then you can refer to the detailed slides in the Appendix. * This section is provided as a quick review. The