Dynamically Parameterized Architectures for Power Aware Video用于功率感知的视频的动态参数化结构.pptVIP

下载本文档

3
0
约6.63千字
约 19页
2017-02-13 发布于上海
举报
版权申诉

Dynamically Parameterized Architectures for Power Aware Video用于功率感知的视频的动态参数化结构.ppt

1、本文档共19页，可阅读全部内容。
2、原创力文档（book118）网站文档一经付费（服务费），不意味着购买了该文档的版权，仅供个人/单位学习、研究之用，不得用于商业用途，未经授权，严禁复制、发行、汇编、翻译或者网络传播等，侵权必究。
3、本站所有内容均由合作方或网友上传，本站不对文档的完整性、权威性及其观点立场正确性做任何保证或承诺！文档内容仅供研究参考，付费前请自行鉴别。如您付费，意味着您自己接受本站规则且自行承担风险，本站不退款、不进行额外附加服务；查看《如何避免下载的几个坑》。如果您已付费下载过本站文档，您可以点击这里二次下载。
4、如文档侵犯商业秘密、侵犯著作权、侵犯人身权等，请点击“版权申诉”（推荐），也可以打举报电话：400-050-0827(电话支持时间：9:00-18:30)。
5、该文档为VIP文档，如果想要下载，成为VIP会员后，下载免费。
6、成为VIP后，下载本文档将扣除1次下载权益。下载后，不支持退款、换文档。如有疑问请联系我们。
7、成为VIP后，您将拥有八大权益，权益包括：VIP文档下载权益、阅读免打扰、文档格式转换、高级专利检索、专属身份标志、高级客服、多端互通、版权登记。
8、VIP文档为合作方或网友上传，每下载1次，网站将根据用户上传文档的质量评分、类型等，对文档贡献者给予高额补贴、流量扶持。如果你也想贡献VIP文档。上传文档

Using System-on-a-Chip as a Vehicle for VLSI Design Education Andrew Laffely and Wayne Burleson Electrical and Computer Engineering University of Massachusetts Amherst {alaffely,burleson}@ Challenges in VLSI Education Advancing Processing Technology Higher level design tools Realistic yet tractable design projects Preparation for jobs in semiconductor and other sectors. Making best use of faculty/student time and university resources ECE 559/659: VLSI Design Project (10 grads, 20 seniors) Learn design process for a complex VLSI in deep sub-micron CMOS Learn VLSI design skills and tools, including working in teams Learn about a particular application component and its VLSI implementation Learn to present formal design reviews using oral, written, graphical and web-based techniques Key Aspects of the Course aSoC (home-grown SoC platform) Provides a unifying framework to class Allows for subdivision but inter-relation of projects Interesting cutting edge architecture based on NSF- and SRC-funded research at UMASS and elsewhere Covers many aspects of VLSI Design Realistic constraints on area, timing, power and I/O Graduate and undergraduate teamwork Graduate students provide leadership, motivation and experience Commercial tools and design flow Review-based evaluation Oral and web-based reports for 4 different reviews: proposal, feasibility, implementation, integration Adaptive System-on-a-Chip (aSoC) Tiled architecture with mesh interconnect Point to point communication pipeline Allows for heterogeneous cores Differing sizes, clock rates, voltages Low-overhead core interface for On-chip bus substitute for streaming applications Based on static scheduling Fast and predictable Communication Interface Custom design to maximize speed and reduce power Core-ports Crossbar Controller Instruction memory Local frequency and voltage supply Class Projects SoC Infrastructure1,3 Communication Interface Interconnect3 Power Distribution Clock System Power Management Cor