clocklesslogic.pptVIP

Clockless Logic Montek Singh Tue, Mar 21, 2006 Dynamic Logic Pipelines (contd.) Drawbacks of Williams’ PS0 Pipelines Lookahead Pipelines High-Capacity Pipelines Drawbacks of PSO Pipelining Poor throughput: long cycle time: 6 events per cycle data “tokens” are forced far apart in time Limited storage capacity: max only 50% of stages can hold distinct tokens data tokens must be separated by at least one spacer Our Research Goals: address both issues still maintain very low latency Recent Approaches 3 novel styles for high-speed async pipelining: MOUSETRAP Pipelines [Singh/Nowick, TAU-00, ICCD-01] “Lookahead Pipelines” (LP) [Singh/Nowick, Async-00] “High-Capacity Pipelines” (HC) [Singh/Nowick, WVLSI-00] Goal: significantly improve throughput of PS0 Two Distinct Strategies: LP: introduce protocol optimizations “shave off” components from critical cycle HC: fundamentally new protocol greater concurrency: “loosely-coupled” stages Outline New Asynchronous Pipelines: MOUSETRAP Pipelines Lookahead Pipelines (LP) High-Capacity Pipelines (HC) Lookahead Pipeline Styles Singh/Nowick Async-2000 Lookahead Pipelines: Strategy #1 Use non-neighbor communication: stage receives information from multiple later stages allows “early evaluation” Lookahead Pipelines: Strategy #2 Use early completion detection: completion detector moved before stage (not after) stage indicates “early done” in parallel with computation Lookahead Pipelines: Overview 5 New Designs: “Dual-Rail” Data Signaling: LP3/1: “early evaluation” LP2/2: “early done” LP2/1: “early evaluation” + “early done” “Single-Rail” Bundled-Data Signaling: LPSR2/2: “early done” LPSR2/1: “early evaluation” + “early done” Dual-Rail Design #1: LP3/1 Optimization = “early evaluation” each stage has two control inputs: from stages N+1 and N+2 Idea: shorten precharge phase terminate precharge early: when N+2 is done evaluating LP3/1 Protocol PRECHARGE N: when N+1 completes evaluation EVALUATE N: when N+2 completes