verilog 分频器,0s计数器及交通灯控制器设计verilog 分频器,30s计数器及交通灯控制器设计.docVIP

分频器 module div(clk, div1,div2,div3); input clk; output div1; output div2; output div3; reg [31:0] counter1; reg [31:0] counter2; reg [31:0] counter3; reg div1; reg div2; reg div3; initial begin div1=0;div2=0;div3=0; counter1=0;counter2=0;counter3=0; end always @(posedge clk) begin /*if(counter1==2) counter1 = 0;else counter1 = counter1+1; if(counter2==3) counter2 = 0;else counter2 = counter2+1; if(counter3==4) counter3 = 0;else counter3 = counter3+1;*/ if(counter1= counter1 = 0;else counter1 = counter1+1; if