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Testing in the Fourth Dimension eng在第四维度测试工程师.auburn.ppt

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Testing in the Fourth Dimension eng在第四维度测试工程师.auburn

Lecture 5: Logic Simulation Lecture 5: Logic Simulation Copyright 2001, Agrawal Bushnell Lecture 5: Logic Simulation * VLSI TestingLecture 5: Logic Simulation Dr. Vishwani D. Agrawal James J. Danaher Professor of Electrical and Computer Engineering Auburn University, Alabama 36849, USA vagrawal@ /~vagrawal IIT Delhi, July 26, 2012, 3:00-4:00PM Copyright 2001, Agrawal Bushnell Lecture 5: Logic Simulation * Contents What is simulation? Design verification Circuit modeling True-value simulation algorithms Compiled-code simulation Event-driven simulation Summary Copyright 2001, Agrawal Bushnell Lecture 5: Logic Simulation * Simulation Defined Definition: Simulation refers to modeling of a design, its function and performance. A software simulator is a computer program; an emulator is a hardware simulator. Simulation is used for design verification: Validate assumptions Verify logic Verify performance (timing) Types of simulation: Logic or switch level Timing Circuit Fault simulation (Lecture 6) Copyright 2001, Agrawal Bushnell Lecture 5: Logic Simulation * Simulation for Verification True-value simulation Specification Design (netlist) Input stimuli Computed responses Response analysis Synthesis Design changes Copyright 2001, Agrawal Bushnell Lecture 5: Logic Simulation * Modeling for Simulation Modules, blocks or components described by Input/output (I/O) function Delays associated with I/O signals Examples: binary adder, Boolean gates, FET, resistors and capacitors Interconnects represent ideal signal carriers, or ideal electrical conductors Netlist: a format (or language) that describes a design as an interconnection of modules. Netlist may use hierarchy. Copyright 2001, Agrawal Bushnell Lecture 5: Logic Simulation * Example: A Full-Adder HA; inputs: a, b; outputs: c, f; AND: A1, (a, b), (c); AND: A2, (d, e), (f); OR: O1, (a, b), (d); NOT: N1, (c), (e); a b c d e f HA FA; inputs: A, B, C; outputs: Carry, Sum; HA: HA1, (A, B), (D, E); HA: HA2, (E